Very-large-scale integration (VLSI) design teams strive to build high ‘quality of result’ (QoR) products. One way to increase QoR is by exploring a large design space during the synthesis stage. However, the backend flow (described further below) may take a long time (days) to complete and, thus, evaluate a final post route QoR from the synthesis stage. Therefore, it is important to be able to predict QoR in the synthesis stage, or earlier stages of the backend flow.
One challenge of predicting post route QoR, such as the path delay between two sequential points from the synthesis stage, is that the paths at the synthesis stage are not the same as those at the post route stage. The backend design flow may change these combinational paths. It may place all the gates and route all the nets. It may also add buffers, resize gates, and change the circuit structures. In the end, the combinational paths may be significantly different to those at the synthesis stage. The large routing parasitic created by routing through congested regions may also make wire load different between the post route and the synthesis stages. These issues create a problem for the design space exploration process because the timing analysis at the synthesis stage cannot accurately estimate the timing at the post route stage.
Another problem is that synthesis optimization based on its own timing analysis might not achieve the optimal results either, because it might work on the wrong critical paths. Conventional solutions include physical design at the synthesis stage, for example, integrating congestion estimation in the synthesis stage. However, these solutions are time consuming and do not provide an accurate prediction of all potential changes to the netlist in the backend flow.